(a) Field of the Invention
The present invention relates to a switching mode power supply (SMPS) for supplying power by switching of a switch.
(b) Description of the Related Art
An SMPS is a device for converting a DC voltage into a square wave voltage by using a semiconductor device (such as a power MOSFET) as a switch, and then acquiring a DC voltage controlled through a filter. An SMPS is more efficient and durable compared to a conventional linear power supply since it controls power by using a semiconductor device as a switching regulator. In addition, an SMPS is a stabilization power device, having small size and less weight as advantages. An SMPS may be applied to industrial fields, including communication devices, computers, OA devices, and home appliances. In general, an SMPS controls the current (the drain current of a MOSFET) flowing to the main switch of the primary coil and maintains the output voltage of the secondary coil through a turn on/off operation of the main switch of the primary coil according to the current output to the load from the SMPS. In this instance, the SMPS feeds the output voltage back to a capacitor of the primary coil, and controls the duty cycle of the main switch of the primary coil through the feedback voltage charged in the capacitor of the primary coil to thereby maintain the output voltage. That is, the SMPS reduces the feedback voltage charged in the capacitor when the current output to the load is reduced to increase the output voltage, and the SMPS increases the feedback voltage charged in the capacitor when the current output to the load is increased to reduce the output voltage.
FIG. 1 is a diagram illustrating a variation of the sense voltage (Vsense) representing the drain current (Ids) flowing through the main switch of the primary coil when an overload condition occurs in a conventional SMPS. The sense voltage (Vsense) is generated when the drain current (Ids) of the main switch of the primary coil flows through a resistor (Rsense). As shown in FIG. 1, the current flowing through the main switch of the primary coil (as represented by sense voltage (Vsense)) increases when the main switch of the primary coil is turned on because of periodic signals from an oscillator. The main switch of the primary coil is turned off when the sense voltage (Vsense) of the main switch of the primary coil reaches the control voltage (Vc).
The current flows to the load through a diode of the secondary coil when the main switch of the primary coil is turned off. In this instance, the control voltage (Vc) is used to control the level of the sense voltage (Vsense) of the main switch of the primary coil, and it functions to maintain the output voltage (Vo). That is, when the current (Io) output to the load is increased to reduce the output voltage (Vo), the feedback voltage (VFB) charged in the capacitor (CFB) of the primary coil is increased, the control voltage (Vc) is gradually increased within the threshold voltage range of Vcsat voltage level in correspondence to the feedback voltage (VFB) to increase the current (Ids) flowing through the main switch.
Therefore, as shown in FIG. 1, the level of the control voltage (Vc) is maintained when the current (Io) applied to the load is constant from the time 0 to T1 on the time axis. In this instance, when the load is increased at the time T1, the current (Io) increases and the output voltage (Vo) of the secondary coil is reduced, thereby causing an overload condition. The control voltage (Vc) level is increased, and the sense voltage (Vsense) is gradually increased until the time T2. In this instance, the slope of the drain current (Ids) of the main switch of the primary coil and the slope of the current (Id) flowing through the diode of the secondary coil are in proportion to the voltage as expressed in Equation 1.
                                          ⅆ            i                                ⅆ            t                          =                  V          L                                    (                  Equation          ⁢                                          ⁢          1                )            
Since the input voltage of the primary coil is generally constant, the rising slope of the drain current (Ids) of the main switch of the primary coil is maintained by Equation 1 when the main switch of the primary coil is turned on. When the current (Io) applied to the load is increased, the output voltage (Vo) of the secondary coil is reduced, and the slope of the drain current (Ids) of the main switch of the primary coil is gradually decreased when the main switch of the primary coil is turned off.
Therefore, the main switch of the primary coil is repeatedly turned on/off because of the signal periodically output by the oscillator. As shown in FIG. 1, the rising slope of the sense voltage (Vsense) becomes greater than the falling slope, and the sense voltage (Vsense) is increased corresponding to the control voltage (Vc) after the time T1 each time the main switch of the primary coil is turned on. However, as further shown in FIG. 1, the control voltage (Vc) has the Vcsat voltage as a threshold voltage. Therefore, after the time T2, the main switch of the primary coil is turned off when the voltage (Vsense) is increased to the Vcsat voltage in the case in which an overload condition is generated and the feedback voltage (VFB) is increased.
The main switch of the primary coil is shut down when the feedback voltage (VFB) is increased to the protection voltage (Vp). The protection voltage (Vp) is a reference voltage for protecting the circuit when an overload is generated. As shown in FIG. 1, when the feedback voltage (VFB) is increased to the protection voltage (Vp) at time T3, the main switch of the primary coil is shut down. In this instance, the period from the time T2 (in which the sense voltage (Vsense) is increased to the Vcsat voltage) to the time T3 (in which the main switch of the primary coil is shut down) may be considered a delay time (Tdelay), which is expressed in Equation 2.
                              T          delay                =                                            C              FB                        ×                          (                                                V                  P                                -                                  V                  c                  sat                                            )                                            I            delay                                              (                  Equation          ⁢                                          ⁢          2                )            
Here, Idelay is the current flowing to the capacitor (CFB) during the delay time (Tdelay). Accordingly, when an overload condition is generated in the conventional SMPS, the main switch of the primary coil is shut down when the delay time (Tdelay) is passed, and hence, the circuit is protected by terminating the operation of the main switch.
FIG. 2 is a diagram illustrating a variation of the sense voltage (Vsense) for representing the current (Ids) flowing to the main switch of the primary coil when an output short is generated for a conventional SMPS. As shown in FIG. 2, at the time T1, the load is increased, which substantially increases the current (Io) applied to the load. The output voltage (Vo) of the secondary coil becomes 0V to thus generate the output short condition. The falling slope of the sense voltage (Vsense) becomes 0 according to Equation 1 when the main switch of the primary coil is turned off. Therefore, the sense voltage (Vsense) for the drain current (Ids) of the main switch of the primary coil is continuously increased each time the main switch of the primary coil is turned on.
FIG. 3 is a diagram illustrating an extended drawing of the sense voltage (Vsense) when the main switch of the primary coil is turned on for a conventional SMPS. Although not illustrated in FIG. 1 and FIG. 2, in the sense voltage (Vsense) waveform, a leading edge overshoot is generated to instantly generate a peak voltage (PC) when the main switch of the primary coil is turned on. Therefore, during the time Tmin in which the peak voltage (PC) is generated, a leading edge blanking (LEB) process is performed so that an excess voltage is not sensed when the sense voltage (Vsense) exceeds the control voltage (Vc) and the main switch of the primary coil is not turned off. Hence, as shown in FIG. 2, when the sense voltage (Vsense) is greater than the Vcsat voltage, the main switch of the primary coil is turned on during the time Tmin for performing the LEB process and the sense voltage (Vsense) is further increased. Therefore, as to the output short condition, the sense voltage (Vsense) is not decreased when the main switch of the primary coil is turned off, differing from the overload condition.
As a result, when the sense voltage (Vsense) becomes greater than the Vcsat voltage, the sense voltage (Vsense) is consecutively increased during the time Tmin when the main switch is turned on. However, in the prior art, in a manner similar to the overload condition, the main switch of the primary coil is shut down after the output short is generated and the delay time (Tdelay) is passed, but the circuit elements may be damaged because a large overload is applied during the delay time (Tdelay).
The above information disclosed in this Background section is only for enhancement of understanding of the invention and is not an admission that such information is in the prior art that is already known in this country to a person of ordinary skill in the art.